The subject CMOS phase interpolation system is generally directed to a system for incorporating a predetermined phase shift into a periodic signal. More specifically, the subject CMOS phase interpolation system generates from one or more reference clock signals a suitably phase shifted clock signal whose duty cycle is adaptively corrected to remain substantially at a desired level.
Phase interpolator circuits find use in a wide variety of applications where fine phase adjustments are necessary in the generation of timing signals, such as digital clock signals. Phase interpolator circuits are employed in the clock data recovery (CDR) carried out, for example, in Serializer-DeSerializer (SerDes) systems to smoothly shift the phase of a recovered clock signal to a selected point within a full 360° range of phase rotation. Typically, the phase of the recovered clock signal in these applications is set to an interpolated value falling at or between phase-separated versions of a given clock signal which serve in the first instance as the reference signals. The operational flexibility afforded by such phase interpolator circuits even allows for the generation of a recovered clock signal that is effectively offset in frequency from a reference clock by continuously rotating its phase through multiple cycles.
Generally, two types of phase interpolator architecture are typically employed: current mode logic (CML) and complimentary metal oxide semiconductor (CMOS) logic. In phase interpolator circuits of the CML type, in-phase and quadrature clocks, along with their complements, are used as the reference clocks. These clocks are applied to switch on and off differential pairs of transistors coupled to weighted current sources. Four differential pairs are used typically to generate an output phase value interpolated between any adjacent two of four reference phases corresponding to the differential pairs, namely, 0°, 90°, 180°, and 270°.
A significant drawback of the CML approach is that they tend to require generally higher supply voltages than may be available in certain applications. Another drawback is that a CML phase interpolator effects smaller signal swing than those using CMOS logic. Consequently, in order to preserve compatibility with CMOS logic employed in other surrounding circuitry or other downstream circuitry, translation of a CML phase interpolator's signal swing to CMOS-compatible levels is normally required. This translation often becomes an unwanted source of jitter and duty cycle distortion in the phase interpolated signal.
CMOS phase interpolators heretofore known also suffer from significant drawbacks. First, the maximum frequency realizable in the phase interpolated clock signal is limited by the excessive number of gates that the given timing signal must propagate through to maintain proper control over such factors as reset time and state transitions. With the gate densities attained using 90 nm CMOS process technology, for example, CMOS-type phase interpolators heretofore known encounter difficulty generating clocks ranging in frequency beyond about 1 GHz. Even that range exceeds the reach of CMOS interpolators implemented at smaller scale CMOS process technologies, such as at 65 nm and 40 nm scale.
Another drawback of the CMOS type phase interpolators heretofore known is their requirement for dual phase interpolator circuits to maintain a clock having somewhere near 50% duty cycle. Aside from the undue complexity added by the additional circuitry, known techniques fail to maintain effective control over the clock's duty cycle. Consequently, an extraneous duty cycle correction circuit is additionally required for typical CDR applications using dual phase interpolator circuitry. There is, therefore, a need for a phase interpolator system that is implemented in CMOS to preserve the power efficiencies and other general advantages of CMOS logic, but which overcomes the practical drawbacks of such implementation. There is a need for a CMOS phase interpolator system which minimizes the number of gates required in the signal path to generate clock signals of higher frequency than in comparable systems heretofore known. There is a need for such CMOS phase interpolator systems equipped with suitable measures to simply and accurately maintain the generated clock signal substantially at a desired duty cycle.